HARDWARE SYSTEM REQUIREMENTS
Pentium 4 or equivalent, 2 GHz or better
PCI motherboard or passive backplane with 3.3V ATX power supply
PCI 2.2 bus
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TECHNICAL SPECIFICATIONS
Max boards per system: Any combination up to 512 ports
Max ports per system: Up to 512 ports
Resource Sharing Bus: MVIP ot H.100
Board Status: On-board LEDs
Clocking: Master/Slave
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ENVIRONMENTAL CONDITIONS
Operating Temperature: 0C to +60C
Storage Temperature: -20C to +85C
Humidity: 8% to 80% non-condensing
Storage humidity: 8% to 80% non-condensing
TELEPHONY INTERFACE
Trunk type: T1/E1
Trunk Interface: Digital High Impedance (Z)
AC Impedance: 1k Ohms |
POWER REQUIREMENTS
+3.3 VDC: 3 Amp
+5 VDC: 5 mA
-12 VDC: Not Required
+12 VDC: 20 mA
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PHYSICAL CHARACTERISTICS
Form Factor: Full-size PCI card
HOST INTERFACE
Bus Compatibility: Complies with PCISIG Bus Specifications, Rev. 2.2
Bus Speed: 33 MHz
Bus Mode: 32 bit bus master/target
OPERATING SYSTEMS
Windows Server 2003 · Windows 2000 · Windows XP · Linux (Call for availability)
ROBBED BIT T1
Signaling Mechanism: AB bits and MF/DTMF digits reported per channel.
Inbound and outbound signaling bits and digits are reported separately.
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DIGITAL TRUNK INTERFACE
Receive clock rate:
1.544 MHz +/-200ppm (2.048 +/-175ppm)
Input level:
3.2 V down to 0.45V (LBO 0 dB to -22 dB)
Input impedance: 1000 Ohm +/- 5%
Maximum tap length: 30 m (100 feet) of CAT 3 cable
Framing: SF (D3/D4), ESF, CRC-4
Line Coding: AMI, B8ZS, HDB3
Clock and data recovery:
Complies with AT&T TR62411 and Bellcore TA-TSY-000170
Connectors:
Two RJ-48C connectors Telephony bus connector:
MVIP-40 pin .025 sq. pin / Dual row
H.100-68 pin fine pitch card edge connector
Loss of Signal Detection:
Per ITU-T G.775 and ANSI T1.231
Alarm Detection and Integration:
Red, Yellow and AIS, per ANSI T1.231
Binary Sequence Detector:
Per ITU-T O.151 |
AUDIO SIGNAL
Receive range: -68 dBm to + 3 dBm
Input gain control: +24 to -64 dB
Silence Detection: Programmable from API
Transmit volume control: +24 to -50 dB
Automatic Gain Control (AGC) Programmable from API
Automatic Volume Control (AVC) Programmable from API
Activity Detection Programmable from API
Alert Tone Programmable from API
ISDN PROTOCOLS
4ESS/5ESS
DMS-100
ETS300 (Euro ISDN)
NI-2
Q.SIG
INS1500
Austel TS014, DASS 2
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AUDIO DIGITIZING (ENCODING & DECODING)
8 Kb/s: G.729A (DP3209 and DP6409 only)
13 Kb/s: GSM 6.10, Microsoft GSM
16 Kb/s: G.726
24 Kb/s: G.726, OKI
32 Kb/s: G.726, OKI
40 Kb/s: G.726
64 Kb/s:
µ-law or A-law per G.711, 8 bit linear PCM
128 Kb/s: 16 bit linear PCM
Wave file formats:
Microsoft GSM, 16-bit PCM, Unsigned 8-bit
Digitization selection:
Programmable per channel, independent for encode and decode
TRIGGER CONDITIONS
Voltage Change Fixed Thresholds
VOX trigger Min/Max silence · Min/Max activity
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DTMF TONE DETECTION
DTMF digits: 0 - 9, *, #, A, B, C, D
Dynamic range: -38 dBm to 0 dBm
Minimum tone detection: 40 ms
Interdigit timing: 40 ms min.
Acceptable twist:
Per LSSGR sec. 6, 8 dB forward, 4 dB reverse
Frequency variation:
Accept all +/- 1.5%, reject all +/-2.5%
Noise tolerance: Per LSSGR sec. 6
Talk off: Bellcore TR-TSY-000762 |
MF R2 SIGNALING · DTMF CAS SIGNALING
MF R2 Digits:
All 15 digits, forward and reverse per Q.441
DTMF Digits: All 16 digits
Signaling Mechanism Supported:
ABCD bits and DTMF digits reported per channel.
Dynamic range for detection:
-25 to 0 dBm per frequency
Acceptable twist: 10 dB
Acceptable frequency variation: 1%
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SAFETY AND CERTIFICATIONS
Telecom: DOC
Emissions: FCC Part 15 class A · EN 55022
Immunity: EN 55024
Safety: EN 60950
Estimated MTBF: 250,000 hours per Bellcore Method I
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© 2005 Ai-Logix Inc. All rights reserved.
公司聲明 |
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